Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ or 133 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. An extended form of SDRAM that can transfer a data value on the rising and falling edge of the clock signal is called double data rate SDRAM (DDR SDRAM, or simply, DDR).
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a Flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a Flash BIOS.
A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells may include a field-effect transistor capable of holding a charge, for instance by use of a floating gate or a structure capable of trapping a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration or each is arranged. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines and their drains are coupled to column bit lines. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. The row of selected memory cells then place their data values on the column bit lines by flowing different currents depending on if a particular cell is in a programmed state or an erased state.
NAND is suited for high capacity data storage, while NOR is suited for code storage and execution, usually in small capacities. NOR offers eXecute In Place (XIP) capabilities and high read performance, but suffers from extremely low write and erase performance. NOR is typically used for code storage and execution, mainly in capacities up to 4 MB common in applications such as simple consumer appliances, low-end cell phones and embedded applications. NOR typically is available in capacities of generally 1 MB-2 GB, and more cost effective in the lower capacities.
On the other hand, NAND architecture offers extremely high cell densities and high capacity, combined with fast write rate and erase rate. NAND is mostly used for data storage in memory cards (e.g., CF, SD, MMC, PCMCIA). NAND-based devices may include a separate NOR memory to store code for execution.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a column bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates of the unselected memory cells of each group are driven to operate the unselected memory cells of each group as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled group, restricted only by the selected memory cells of each group. This places the current encoded data values of the row of selected memory cells on the column bit lines.
At high densities, the cost of NAND memories is significantly less than NOR devices of comparable density. This cost differential makes NAND devices increasingly attractive for embedded applications in which NOR devices are typically used. At lower densities (e.g., under 128 MB), NOR is still attractive from a cost perspective.
As memory manufacturers continue to innovate and create, a serial interface is increasingly attractive as offering several benefits over the parallel interface in reducing overall systems costs including microcontroller and chipset pin-count reduction, smaller and simpler printed circuit boards, and lower power consumption.
Serial flash memory is an attractive solution for a variety of applications. Serial memories are popular because of their efficient signal interface and cost effective packages. The serial interface offers several benefits over the parallel interface in reducing overall systems costs including microcontroller and chipset pin-count reduction, smaller and simpler printed circuit boards, and lower power consumption.
A serial interface using the Serial Peripheral Interface (SPI) bus has gained significant industry acceptance for its low pin count (as low as 4 active signals) and high clock rates (running in excess of 100 MHz). The SPI bus is often used in designs where low cost is important.
An SPI system includes one master device and one or more slave devices that communicate using the SPI bus. The master is a microcomputer providing the SPI clock, and the slave is an integrated circuit that receives the SPI clock from the master. The slave may include one or more SPI memory devices, which allow for smaller die sizes and smaller packages, and lowered pin count, compared to non-SPI-based memory devices.
Some types of memory technology have a variable period of time between receipt of an address from which to read the memory, and the contents of that memory address being available for transfer from the memory device. For instance, PSRAM devices have longer initial accesses when an internal refresh operation must complete before the read request can be processed. A fixed latency period, if used, would have to be set long enough to accommodate the longest access time of the memory under all circumstances. Any time between the actual access time and the longest access time would be inefficiently used as idle time.
A variable latency can be implemented for the memory device to signal when the memory contents are available to be read from the device. For instance, some PSRAM devices utilize a dedicated signal line to indicate when the PSRAM device is ready to provide the memory contents, to differentiate between slower and longer initial read accesses. In this was a variable latency is provided. However, the dedicated signal line increases the size, pin count, and interconnect cost of the memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a variable read latency on a serial memory bus, such that a dedicated signal line is not used.